• 52 pin PLCC package
• 8 Channel, 8 bit resolution A/D
• Serial Communications Interface
• Serial Periferal Interface
• 5 output timer channels, 3 input timer channels
• 512 bytes EEPROM
• 512 bytes RAM

EPROM

The board supports one 28 pin EPROM of sizes 8K (2764), 16K (27128) or 32K (27256) bytes. The type is selected by jumpers. The EPROM supplied with the kit is pre-programmed with a monitor program and the floating point math package.

RAM

The board supports one 28 pin RAM, sizes 8K and 32K. The RAM type is selectable by jumpers.

Input Register

One eight bit parallel output latch, type 74HC273, is mapped into the memory address space. The output lines are connected to a header.

LCD Display

A header is supplied for attachment of an LCD display. A 2 line by 16 character or 2 line by 20 character display is included with the kit. The LCD display is mapped into the memory space of the microprocessor. Notice that the LCD display attached to this port is only guaranteed to work with a 1MHz E Clock (4MHz crystal), though we've never found a problem using an 8 MHz cyrstal (2MHz E Clock).

Memory Map Decoder

The memory map is decoded by a 16V8 GAL device, which is supplied programmed with the default memory map. Outputs of the decoder select the EPROM, RAM, Input register, Output Register, and the LCD display header. The GAL also converts the Motorola style control lines (Enable, R/W) into Intel style control lines Write Enable, Read Enable) for use by the various periferals.

Reset Circuit

A momentary action pushbutton is provided on the board for reset. A LVI (low voltage inhibit) device ensures correct reset of the board under power-on conditions.

Power Supply

The board includes a 5 volt regulator with room for a small heat sink if required. The unregulated power input connection is via a power coaxial jack which mates with a 9 volt, 500 mA DC adaptor wall wart power supply. The unregulated power input connection includes a power diode to prevent the reverse application of power. The raw 9 volts is brought to a pad or terminal to support the powering of single supply op amps from a supply greater than +5 volts. Bipolar power of +/-10 volts and a few milliamps is available from the RS232 level converter. This might be useful to power one or two op amps or other low current devices that require bipolar power.

Wire Wrap Area

Unused board area is a matrix of holes on 0.1 inch centres for application-specific circuitry.

Bus Expansion Header

This connector may be used to attach memory mapped periferals. For example, video memory could be mapped into the address space using this connector and the Select0 address decode signal. The signals that are brought to the Bus Expansion Header are:

* AD[7..0]
* A[11..8]
* Select0
* Address Strobe
* Reset
* Read
* Write
* +5VDC
* Ground
* Spare (3 pins)

The spare pins can be jumpered to signals (such as IRQ) to suit the project. Examples of interfacing to the Bus Expansion Header are given in the Technical Manual (on CDROM).

Crystal

The kit is supplied with a 4MHz crystal. Either a 4MHz or 8MHz crystal may be used, but the LCD port should be used with a 4MHz crystal.

Serial Port

A PCB mount DB-9 connector on the board is configured for a direct serial (COM) port connection to a PC. (No crossovers or null modem required.) Three wire RS232 connection. No handshaking, 4800 baud, 8N1. A Maxim MAX232 or Linear Technology LT1081 translates the 5 volt logic signals to and from the RS-232 logic swing and helps isolate the microprocessor board from the P/C development system.

Synchronous Port Interface

The SPI is one of several ways to connect external devices to the microprocessor, either to sense external signals or generate signals to control other devices. The following signals are brought out to a header to
facilitate use of the SPI.

* MISO (PD2)
* MOSI (PD3)
* SCK (PD4)
* SS* (PD5)

Pullups on 68HC11 Pins

The following pins are pulled up by resistors to +5 volts: XIRQ, IRQ, MODA, MODB, IC1, IC2, IC3. Each pin has an associated wire wrap terminal to which signals may be connected. A-D Inputs Inputs to the A-D, VRH and VRL are brought out to wire wrap pins. VRH is not connected to +5 volts, and VRL is not connected to ground, since they should be connected to the analog section of the project. For non-critical A-D pplications, the VRH and VRL pins may be jumpered to +5 volts and ground. LED Indicators Three LEDs are provided to indicate the board status and help diagnose problems:

* Power
* Serial port transmit
* Serial port receive

Single Stepping

In order to support single stepping operation using the Buffalo monitor, OC5 is connected to XIRQ. Two adjacent header pins are provided for this purpose: jumpering them connects OC5 to XIRQ.

Overall size

4.5" x 6.25" (11.5 cm x 16 cm)

MPP Default Memory Map

The memory map for a computer system shows the addresses of the various
hardware devices and resident software. The default memory map for the MPP
system is shown in the figure.

The following devices are memory mapped:

EPROM

The EPROM may have three different sizes: 8k,16k or 32k bytes. In all cases,
the end of the EPROM must occur at the top of memory in order to store the
processor reset vectors. Thus the starting address of an EPROM depends on
its size. The default memory map decoder enables the EPROM select line for
the upper half of memory, so that any sized EPROM will work without changes
to the GAL. The EPROM supplied with the MPP board kit is preprogrammed with
the 8k Buffalo Monitor and 3k MATH11 routines.

RAM

The static RAM may have two different sizes, 8K or 32K bytes. In order to be
compatible with the three different sizes of EPROMs, the RAM is located in
the bottom half of memory. A 32K byte RAM overlaps a variety of things in
the bottom half of memory, and so is effectively not useable below address
$1800.

An 8K or 32K RAM chip may be used without changes to the decoder GAL.

LCD Display

The base address of the LCD display is established at $1400.

Input-Output Registers

These are both located at a base address of $1100. A write directs the data
to the output register: a read gates the input register onto the data bus.

Select0

One additional spare device select line is available from the GAL decoder
circuit and brought out to the bus expansion connector.